1. Field of the Invention
This invention relates generally to data processing systems and more particularly to the memory unit of such systems which is used for storing the signal groups required for the current operation of the data processing system.
2. Description of the Related Art
Referring to FIG. 1, a typical data processing system configuration is shown. The illustrated data processing system includes central processing units 10 and 11, input/output units 13 and 14, a main memory unit 15, and a system bus 19 coupling together the central processing, input/output, and main memory units of the data processing system. The central processing unit 10 or 11 processes groups of logic signals according to software and/or firmware instructions. The logic signal groups to be processed as well as the currently executing program are typically stored in the main memory unit 15.
A console unit 12 can be coupled to the central processing units and includes apparatus and stored instructions to initialize the system. The console unit 12 can also act as a terminal during the operation of the data processing system. The input/output units 13 and 14 provide a user interface to the remainder of the data processing system components such as terminal units, mass storage units, communication units, and any other units to be coupled to the data processing system.
The detailed function of the units coupled to the system bus 19 is less important to an understanding of the present invention than the fact that these units operate autonomously and communicate with the remainder of the data processing system units by means of the system bus 19. In particular, the system bus 19 is used to store signal groups into and to retrieve signal groups from the main memory unit 15 by the other units.
Referring next to FIG. 2, a block diagram of a typical main memory units 15 found in the related art is shown. The main memory unit 15 includes a memory interface unit 21 that exchanges signals with the system bus 19. The memory interface unit 21 is coupled to a memory unit bus 22 and the memory unit bus 22 has memory array units 23 coupled thereto. The memory array units 23 each comprises a plurality of logic signal storage elements organized in groups so that each group of storage elements can be accessed by a unique logic signal group address.
The memory interface unit 21 includes apparatus for controlling the exchange of logic signal groups, identified by a logic signal group addresses, between the memory array units 23 and the system bus 19. The memory interface unit 21 also includes apparatus for identifying signal activity on the system bus 19 directed to the memory unit 15 as well as to apparatus for returning logic signal groups to the data processing units which had requested specified logic signal groups from main memory 15. Buffering of the data logic signal groups, error correction, and generation of control signals are also typically performed in the memory interface unit 21 in the related art.
The foregoing conventional main memory architecture limits the amount of activity that can be performed in the main memory unit because all activity must be performed under the control of a memory interface unit 21, so only a single activity operation may be performed at one time unless parallel processing apparatus is included for simultaneous processing of a plurality of signal groups.
A need has therefore been felt arisen for apparatus and methods of operation for a main memory unit that can permit multiple simultaneous operations involving that main memory unit. This requirement is particularly stringent in the computer systems referred to as "write through" data processing systems in which each a logic signal group from a central processing unit is immediately stored or written into the main memory unit. The memory activity resulting from write-through data processing systems can result in performance deterioration unless the main memory unit is designed to accommodate the increased activity.